Digital communications involves conveying digital data by generating, sending, receiving, and processing analog waveforms. A transmitter accepts a sequence of digitally formatted data and converts the sequence into an analog waveform. Each time interval of this waveform carries or is encoded with an element of digital information referred to as a symbol. A one-to-one correspondence typically exists between each discrete waveform state and each symbol. That is, for the set of symbols that a communication system can convey, each symbol matches a specific signal level from two or more signal level possibilities. The transmitter outputs the waveform onto a medium or channel. The waveform transmits or propagates over the medium or channel to a receiver, which decodes or extracts the original data from the received waveform.
The transmitter generating the waveform sets the signal amplitude, phase, and/or frequency of the output waveform to one of N discrete values, levels, or states during the time interval to represent digital information. Binary signaling uses N=2 levels, with the levels corresponding to or representing “0” and “1”. Multilevel signaling schemes can use more than two levels, i.e. N≧2, with the levels being “0”, 1, . . . , “N−1”. The transmitter transmits a signal level or symbol during a predetermined time period or interval called the symbol period and denoted as T0. Thus, the transmitter conveys digital data to the receiver as a sequence of symbols, transmitting one symbol per symbol period.
On the opposite end of the communication link from the transmitter, the receiver decodes the digital information from the communicated analog waveform. That is, for each symbol, the transmitter determines or detects which of the levels was transmitted from the N possibilities. Thus, the receiver processes the incoming waveform to assign a symbol to each symbol period. If the symbol that the receiver assigns to the waveform is the same symbol that the transmitter used as the basis for modulating or generating the waveform, then the communication of that symbol succeeded, and that data element transmitted without error.
However, the transmission of data in a physical medium or communication channel is not always error free. The communicated signal can degrade during propagation resulting in data errors. In particular, the transmission channel or transmission medium can distort the waveforms via dispersion or other phenomena resulting in what is known as intersymbol interference (“ISI”). Noise or interference from external sources can also corrupt the signal during transmission, for example exacerbating ISI.
The term “intersymbol interference” or “ISI,” as used herein, refers to signal interference stemming from the transfer of signal or waveform energy from one symbol period to another symbol period. ISI can appear as slight movements of a transmission signal in time or phase, also known as jitter or timing distortion, that may cause synchronization problems. ISI can result from temporal spreading and consequent overlapping of the pulses or waveform segments that occupy each symbol period. The severity of ISI can compromise the integrity of the received signal to the extent that the receiver does not reliably distinguish between the symbols in two adjacent symbol periods or otherwise misidentifies a symbol.
Signal distortion, as well as noise related to ISI and other interference sources, can lead to decoding errors. In some limited circumstances, conventional equalization techniques are available to reduce the incidence of data errors that ISI causes. The term “equalization,” as used herein, refers to manipulating a communication signal in a manner that counteracts or otherwise compensates for signal changes that occur during transmission on a communication channel or medium.
Equalization can be viewed as an intentional “distortion,” applied at either the receiving or the transmitting end of communication link, that counteracts detrimental distortion introduced by the channel. Unfortunately, many conventional equalization techniques (linear equalizers in particular) tend to exacerbate the effect of the noise. Thus, conventional equalizers are often limited in the magnitude of equalization that they can apply. Beyond a certain level of applied equalization, such equalizers can induce or amplify noise, thereby degrading communication integrity. An appropriately-set equalizer based on conventional technology is usually balanced to yield a favorable tradeoff between the amount of ISI removed and the amount of noise amplified.
Decision feedback equalization is a known equalization method that can be applied at the receive-end of a communications system. A decision feedback equalizer (“DFE”) is a nonlinear equalizer intended to remove ISI without exacerbating the noise, thereby permitting a higher level of ISI cancellation and an improved equalized signal. The term “decision feedback equalizer” or “DFE,” as used herein, refers to a device that suppresses ISI in a first time interval of a communication signal by generating a correction signal based on processing a second time interval of the communication signal and applying the correction signal to the first time interval of the communication signal.
FIG. 1 illustrates a functional block diagram of an exemplary conventional DFE 110. The DFE 110 takes as input the communicated signal vrx 120 and applies a corrective signal vfb 130 to suppress or remove ISI. The DFE 110 generates this corrective signal 130 via an internal feedback mechanism based on an arrangement of delay stages 170 and attenuators or amplifiers 180.
The compensated signal vcomp 140 (i.e. received signal 120 plus the applied corrective signal 130) is quantized by the slicer 150 to one of the candidate N signal levels. Specifically, the slicer 150 takes as input a (potentially distorted) multilevel signal 140 and outputs a reconstructed or regenerated multilevel signal 160. The term “slicer,” as used herein, refers to a device that processes an incoming analog signal and outputs a signal having a discrete characteristic that corresponds to at least one element of digital data. For example, a slicer 150 can slice, clip, or set the amplitude of a pulse to provide a resulting signal that has a specified amplitude.
For each symbol period, the slicer 150 sets or forces the signal level of its output 160 to the discrete level or state of the nearest valid symbol of the multilevel signal, thereby removing minor signal degradation. In other words, for each symbol period, the slicer 150 evaluates the incoming signal 140 and manipulates it to provide a discrete signal state that corresponds to one of the symbol possibilities. If the signal degradation is within a range of severities that the conventional DFE 110 can accommodate, the resulting symbol value output by the slicer 150 is the same as the symbol that was transmitted. In other words, within a limited level of signal degradation, the conventional DFE 110 removes noise or signal ambiguity to accurately reconstruct the signal output by the transmitter, thereby providing data transmission without error.
Since the slicer output vout 160 should nominally have the same level as the transmitted signal, the slicer output 160 can be delayed and scaled to model (and subsequently remove) the ISI that this symbol imposes on symbols yet to be received in the communicated waveform. That is, the conventional DFE 110 processes the waveform element in each symbol period based in part on the processing of earlier-received waveform elements.
Referring now to FIGS. 1 and 2, the illustrated conventional DFE 110 provides a plurality of feedback loops 210, each providing a delay δi (small letter “delta”) and an amplification gain ai. Referring specifically to the feedback loop 210 identified in FIG. 2, the delay element 170a delays the quantized signal 160 by an amount of time δ1 such that the cumulative delay through (i) the slicer 150, (ii) the delay element 170a, (iii) the adjustable amplifier 180a, and (iv) the summation nodes 190a and 190b is equal to the symbol period T0. The delay along this path 210 will be referred to as the primary loop delay Δ (capital letter “delta”). Through appropriate setting of the gain a1 on the adjustable amplifier 180a, the ISI from the immediately preceding symbol can be removed when Δ=T0. Referring now to FIGS. 1 and 2, in a similar fashion, setting the delay δk and gain ak on subsequent stages or feedback paths of the DFE 110 can remove ISI from the symbols of other symbol periods.
Thus, the feed back loop 210 through amplifier 180a addresses ISI on a current symbol period resulting from a symbol transmitted in the immediately preceding symbol period. The feedback loop through amplifier 180b addresses ISI on the current symbol period resulting from a symbol transmitted during the time frame that is two symbol periods earlier. Likewise, the Kth feedback loop through amplifier 180c addresses ISI on the current symbol period due to a symbol transmitted during the Kth previous symbol period.
One problem with the conventional DFE 110 lies in implementation feasibility for high-speed multilevel systems with N>2. In these systems, it is often a challenge to build a slicer 150 with a propagation delay sufficiently small to meet the primary loop delay criterion Δ=T0. In certain conventional applications involving relatively slow data rates, conventional DFEs 110 may perform adequately. That is, the slicer propagation delay limitation that most conventional DFEs exhibit may not prevent adequate performance at slow or modest data rates. In particular, at low symbol rates (e.g. thousands or a few millions of symbols per second), the functionality illustrated in FIG. 1 could be realized by sampling the signal with an analog-to-digital converter (“ADC”) and carrying out the DFE operations in a digital signal processor (“DSP”).
However, conventional DFEs 110 are often inadequate for high-speed communication systems, (e.g. systems with symbol rates above 100 million bits per second or on the order of billions of symbols per seconds). It is often impractical to implement a conventional DFE 110 with an ADC and a DSP commensurate with the high symbol rate (i.e. small T0 and hence stringent primary loop delay criterion).
For high-speed systems, conventional DFEs 110 have been built for binary (N=2 levels) systems based on fast integrated circuit (“IC”) processes. With good IC design, the propagation delay criterion can be achieved because the slicer 150 (which is usually the most significant contributor to the first loop propagation delay Δ) corresponds to a simple thresholding device that can be implemented with a small amount of circuitry. In particular, a single comparator or limiting amplifier can perform the slicing function for binary communication as known to those skilled in the art.
Problems can arise when attempting to use conventional technology to implementing a DFE 110 for a high-speed communication system that uses more than two communication signal levels (N>2) to convey data. One approach is to quantize the slicer input 120 by (i) applying an ADC to decode the signal value, followed by (ii) applying a digital-to-analog converter (“DAC”) to regenerate the multilevel signal. This regeneration, however, is problematic because the propagation delay through the combination of the ADC and DAC usually exceeds the aforementioned time criteria for the primary loop 210.
Conventional attempts have been made to increase DFE performance by reducing propagation delay through aspects of the DFE 100 other than the slicer 150. That is, conventional technologies may quicken the computing of the amount of ISI compensation (i.e. vfb 130) based on the slicer output vout 160. However, conventional technologies generally fail to adequately shorten the total propagation delay of the primary feedback loop for high-speed multilevel communication. Thus, for many applications, the net delay of the conventional primary loop path 210, which includes the slicer delay, extends beyond the symbol period and thus is too lengthy. In other words, slow slicing often limits conventional DFEs 110 to addressing ISI on communication signals that convey data with two signal levels or with relatively slow data rates.
U.S. Pat. No. 5,594,756, entitled “Decision Feedback Equalization Circuit” proposes a DFE for high-speed communications systems. The disclosed technology attempts to address the difficulty of quickly estimating the feedback correction component from the slicer output. A disclosed feedback mechanism pre-computes correction components for each of the potential cases of transmitted symbols and uses a switch to select a specific one of these correction components for application. One shortcoming of the technology is that the slicer propagation delay, termed “DET” in that patent's disclosure, generally limits the slicer propagation delay to an unacceptably long time. Thus, for many high-speed applications, the technology of the '756 patent may be inadequate.
U.S. Pat. No. 6,047,026, entitled “Method and Apparatus for Automatic Equalization of Very High Frequency Multilevel and Baseband Codes Using a High Speed Analog Decision Feedback Equalizer,” discloses another DFE approach. The '026 patent proposes a DFE structure utilizing positive and negative portions of slicer output pulses that feed into finite impulse response (“FIR”) filters. The use of both positive and negative components purportedly allows operation at high frequencies in certain circumstances. This patent emphasizes achieving faster generation of the ISI corrective component but fails to disclose adequate slicer technology that provides sufficient speed for many applications. Despite improving the speed of the feedback loop in a DFE, the technology of the '026 patent supports symbol rates generally limited by the propagation delay of the slicer.
U.S. Pat. No. 6,198,420, entitled “Multiple Level Quantizer,” proposes an ADC with automatic dark-level detection for optical communications contexts. The '420 patent discloses using a flash converter in a manner that can be inadequate for many high speed applications. The technology disclosed in the '420 patent is generally limited in its capability to adequately address propagation delay of an ADC. Further, that technology has limitations related to combining the functionality of a DAC and an ADC in a DFE. The disclosed latching mechanisms following each comparator can add significant propagation delay that may encumber the primary feedback loop with excessive aggregate delay. Latching mechanisms have been known to exhibit propagation delays that can exceed one half of the symbol period, for example. As discussed above, a DFE should regenerate multilevel signals (i.e. the function performed by the combination of the ADC and the DAC) in less time that the time span of a symbol period T0. Thus, the technology of the '420 patent may not adequately support many high-speed applications involving multi-level communications.
To address these representative deficiencies in the art, what is needed is a capability to deal with ISI in high-speed multi-level communication systems. A further need exists for a DFE that operates in a communication system that conveys data using more than two signal levels. Yet another need exists for a slicer that quantizes multilevel signals to the candidate symbol values with a propagation delay that is small enough to support setting the primary loop delay Δ in the DFE to the symbol period T0 of the communication system. Such capabilities would reduce ISI effects and facilitate higher bandwidth in numerous communication applications.